The present invention relates to a method of producing a complementary-type semiconductor device and more particularly to MIS(metal insulator semiconductor) transistors such as CMOS(complementary metal oxide semiconductor) transistors having P-type and an N-type channels.
With regard to reduction in size of CMOS-LSI devices, there have been two major problems which are the so-called hot carrier effect which occurs in N-type transistors and the short-channel effect which occurs in P-type transistors. In the prior art, an LDD(Lightly Doped Drain) structure has been proposed and used in CMOS transistors for the purpose of reducing the hot carrier effect. However, such LDD structures have the following problems.
First, according to a process for producing the LDD structure, an N-type diffusion layer has to be formed at only an N-type transistor of a complementary-type MIS transistor and should not be formed at a P-type transistor thereof. Therefore, for the purpose of covering the P-type transistor with a photo-resist, a further process of photo-lithography is required and causes high production cost.
Further, according to a process for producing the LDD structure, spacers have to be formed on the side walls of gate electrodes so as to form different impurity concentration layers within the LDD structure. Such a process also causes high production cost and low productivity.
In view of the above-described problems with regard to the LDD structures, the inventors of the present invention proposed a new type of CMOS structure which was described in a Japanese patent publication laid-open No. 62-217666 published on Sept. 25, 1987 and a counterpart U.S. patent application Ser. No. 26,998 filed on Mar. 17, 1987. However, in the process of producing devices using this CMOS structure, the inventors of the present invention came to notice the following problems.
As shown in FIG. 11, phosphorus ions (P) are implanted through a gate insulating film 102 and a gate electrode 103 of poly-crystalline silicon served as a mask so that an N-type diffusion layer 101 having a low impurity concentration is formed within a silicon substrate 100. In case that a crystal axis of a part 103a of the polycrystalline silicon is nearly the same as the direction of the ion implant, the phosphorus reaches below the gate electrode 103 and an unnecessary N-type diffusion area 104 is partially formed in the silicon substrate 100. This is a so-called channeling phenomenon which causes an occurrence of a leak current and therefore a lower productivity. The probability of the occurrence of such an area 104 is in the range between one in several thousand and one in a million transistors, which is an extremely severe problem in the production of VLSI(Very Large Scale Integration) devices.